Area-Time-Power of Modular Multipliers implemented in FPGA
نویسندگان
چکیده
Three modular multiplication algorithms are described and compared: the so-called Multiply and Reduce, the Shift and Add, and finally, the Montgomery product. An estimation of the cost of their combinational implementation using Xilinx FPGAs family is calculated. Practical results in term of area, delay, and power for both combinational and completely sequential implementations are presented.
منابع مشابه
High Speed Systolic Montgomery Modular Multipliers for RSA Cryptosystems
Montgomery modular multiplication is one of the most important and frequently used techniques to accelerate the time consuming mathematical operations used in RSA cryptosystems. In this paper, a modified Montgomery modular multiplication algorithm is presented where the carry-save operations are split into two cycles so as to eliminate the generation of the data-dependent control signal from do...
متن کاملA Low complexity solution to the implementation of linear periodically time varying filters-FPGA implementation
This paper presents an area efficient architecture for a linear periodically time varying (LPTV) filter. It is developed from the output switching representation of LPTV filter. In this representation, an N-tap,M Period LPTV filter can be realized by M linear time invariant (LTI) filters of N taps each connected in parallel with an M periodic switch at the output. We devloped an area efficient ...
متن کاملFPGA Can be Implemented Using Advanced Encryption Standard Algorithm
This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. This method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theAES InverseSub Bytes module and...
متن کاملSpeed and Area Optimized Parallel Higher-Radix Modular Multipliers
Modular multiplication is the fundamental and compute-intense operation in many Public-Key crypto-systems. This paper presents two modular multipliers with their efficient architectures based on Booth encoding, higher-radix, and Montgomery powering ladder approaches. Montgomery powering ladder technique enables concurrent execution of main operations in the proposed designs, while higher-radix ...
متن کاملRadix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp
This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fp based on interleaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cy...
متن کامل